FIGS. 42(a) and (b) are cross-sectional views each showing a nonvolatile magnetic storage device (a Magnetoresistive Random Access Memory, hereinafter, referred to as an “MRAM”) in a conventional structure, the entire structure of which is indicated by reference numeral 500. FIG. 42(a) is a cross-sectional view showing a single cell, and FIG. 42(b) is an enlarged view showing a TMR (Tunneling Magneto-Resistance) element. The TMR element is also referred to as a MTJ (Magnetic Tunneling Junction) element.
On an interlayer insulating film 23, there are formed an interlayer insulating film 27 as well as a lower electrode (leading line) 28 of a TMR element 50, which is connected to a wiring layer (digit line 24) 25 through a via-hole. On the lower electrode 28, the TMR element 50 and an upper electrode 29 of the TMR element 50 are formed.
As shown in FIG. 42(b), the TMR element 50 is configured by a lower magnetic film 51, an upper magnetic film 52, and a tunnel insulating film 53 sandwiched therebetween.
An inner insulating film 30 is formed on the upper electrode 29. An opening that reaches the upper electrode 29 is formed in the interlayer insulating film 30, and a wiring layer (bit line) 32 is formed therein with a barrier metal layer 132 interposed therebetween.
In a storing operation of the MRAM 500, by applying a composite magnetic field, which is induced by an electric current allowed to flow through the digit line 24 and the bit line 32, to the TMR element 50, while the magnetic direction of the lower magnetic film (pin layer) 51 being fixed, the magnetic direction of the upper magnetic film (free layer) 52 is inverted so that a data writing operation is carried out. Depending on states where the magnetic direction of the upper magnetic film 52 is the same as (parallel to) the magnetic direction of the lower magnetic film 51 and where being opposite (anti-parallel) to the magnetic direction of the lower magnetic film 51, the resistance value of a tunnel current flowing through the tunnel insulating film 53 is made different from each other when the current is allowed to flow through the memory cell 50, and is difference in resistance value corresponds to “0” and “1” in the memory (JP 2004-119478, A).